1. Field of the Invention
The invention relates to a semiconductor device, particularly to a semiconductor device having a MOS transistor and a resistor on the same semiconductor substrate.
2. Description of the Related Art
A semiconductor device in which a MOS transistor and a resistor are mounted on the same semiconductor substrate has been conventionally known. A drive circuit of a vacuum fluorescent display is known as using this semiconductor device. The vacuum fluorescent display is also called VFD (Vacuum Fluorescent Display), and emits light when electrons flowing from a cathode electrode are controlled by a grid electrode and impact a phosphor on an anode electrode in a vacuum chamber. The vacuum fluorescent display is used as a digital display part of an audio system, a watch, an electronic calculator or the like.
This vacuum fluorescent display need a high voltage in the anode electrode and the grid electrode in order to emit light, and the output stage of the drive circuit is generally configured as follows. This output stage of the drive circuit includes a P-channel type MOS transistor (hereafter, referred to as PMOS) 100 connected between an output terminal Out and a power supply voltage VDD and a pull-down resistor 102 connected between the drain side of the PMOS 100 and a negative voltage supply terminal 101, as shown in FIG. 2. A back gate of the PMOS 100 is connected with the power supply voltage VDD. The output terminal Out is connected with a grid electrode and an anode electrode (not shown).
An output signal (a driver signal DRV) of a logic circuit (not shown) is applied to a gate of the PMOS 100, and thereby on and off of the PMOS 100 are controlled. A predetermined voltage (a high level and a low level) is supplied to the grid electrode and the anode electrode by controlling the PMOS 100. The power supply voltage VDD is about 5V, for example, and the negative voltage supply terminal 101 supplies a negative voltage of about −30V to −40V.
Next, the device structure of the PMOS 100 will be described referring to FIGS. 3A and 3B. FIG. 3A is a plan view of the PMOS 100, and FIG. 3B is a cross-sectional view of FIG. 3A along line Y-Y. This PMOS 100 is so configured that a plurality of MOS transistor structures forms one high voltage PMOS 100 as a whole.
As shown in FIGS. 3A and 3B, in a PMOS 100 formation region, an N-type well region 106 is formed in a front surface of a P-type semiconductor substrate 105, and an element isolation insulation film 107 is formed on this well region 106 by a LOCOS method or the like. A plurality of gate electrodes 108 is annularly formed on the front surface of the semiconductor substrate 105 (the well region 106) where the element isolation insulation film 107 is not formed, with a gate insulation film (not shown) interposed therebetween. P−-type low concentration drain regions 109 are formed in the front surface of the semiconductor substrate 105 (the well region 106) in regions surrounded by the gate electrodes 108 respectively, and P+-type high concentration drain regions 110 for contacts are formed in the front surface of the low concentration drain regions 109 respectively. P+-type high concentration source regions 111 corresponding to the low concentration drain regions 109 are formed in the front surface of the semiconductor substrate 105 (the well region 106) on the outside of the annular gate electrodes 108, surrounding each of the gate electrodes 108.
It is noted that conductivity types P+, P, P− and the like belong to one general conductivity type, and conductivity types N+, N, N− and the like belong to another general conductivity type.
An interlayer insulation film 112 is formed on the front surface of the semiconductor substrate 105 including on the gate electrodes 108, and contact portions 113 are formed in this interlayer insulation film 112, reaching the high concentration drain regions 110 and the high concentration source regions 111. Furthermore, wiring layers 114 and 115 are formed in these contact portions 113. The wiring layer 114 is commonly connected with the high concentration source regions 111, and the wiring layer 115 is commonly connected with the high concentration drain regions 110. The wiring layer 114 is connected with the power supply voltage VDD, and the wiring layer 115 is connected with an output terminal Out and one end of the pull-down resistor 102 that will be described below. A driver signal DRV is applied to each of the gate electrodes 108.
Next, the device structure of the pull-down resistor 102 will be described referring to FIGS. 4A and 4B. FIG. 4A is a plan view of the pull-down resistor 102, and FIG. 4B is a cross-sectional view of FIG. 4A along line Z-Z.
As shown in FIGS. 4A and 4B, an N-type well region 120 is formed in the front surface of the semiconductor substrate 105 in a pull-down resistor 102 formation region, and an element isolation insulation film 121 for isolating the pull-down resistor 102 from the other elements (the above-described PMOS 100 or the like) is formed on this well region 120 by a LOCOS method or the like. A P−-type resistor layer 122 is formed in the front surface of the well region 120 surrounded by the element isolation insulation film 121 by implanting a low concentration of P-type impurity therein, and P+-type electrode leading layers 123 are further formed therein like islands by implanting a high concentration of P-type impurity therein.
A P-type impurity ion is implanted between the electrode leading layers 123 opposing each other to form an impurity layer 124 (FP) in order to prevent voltage dependence. Contact portions 125 and 126 are formed on the electrode leading layers 123, and wiring layers 127 and 128 are formed in the contact portions 125 and 126. The electrode leading layer 123 is connected with the drain side of the above-described PMOS 100 and the output terminal Out through the wiring layer 127, and the other electrode leading layer 123 is connected with the negative voltage supply terminal 101 through the wiring layer 128. This technology is described in Japanese Patent Application Publication Nos. H9-26758 and 2003-224267, for example.
However, in the above-described resistor (the pull-down resistor 102), the element isolation insulation film 121 is formed adjacent to the resistor layer 122. Therefore, stress is concentrated on the end of the element isolation insulation film 121, and the degradation of a breakdown voltage may occur between the resistor layer 122 and the well region 120.
Furthermore, since a semiconductor integrated circuit with higher density and higher performance has been developed recently, the area of each of semiconductor elements need be minimized. Therefore, it is preferable to miniaturize the described semiconductor device in which the MOS transistor and the resistor are mounted together.
The invention is directed to providing a resistor with high reliability. The invention is also directed to miniaturizing a semiconductor device in which a MOS transistor and a resistor are mounted together on the same semiconductor substrate.